`include "CP0Defines.svh"
module MEM2_WB (
    input logic clk,
    input logic reset,
    input logic MEM2_WB_Flush,
    input logic MEM2_WB_Stall,

    input logic [31:0]MEM2_PC,
    input logic [31:0]MEM2_NPC,
    input logic [31:0]MEM2_Instr,
    input logic [4:0]MEM2_RW,
    input logic [1:0]MEM2_Data_To_Reg_Sel,
    input logic [31:0]MEM2_ALU_Out,
    input logic [31:0]Data_From_DM_AfterExt,
    input logic MEM2_IsBranch,
    input logic MEM2_Immjump,
    input logic MEM2_CP0Wr,
    input logic MEM2_DMRd,
    input ExceptionType MEM2_ExceptionType,
    input logic [2:0]MEM2_Reg_Writed,
    input logic [31:0]MEM2_CP0RdData,

    output logic [31:0]WB_PC,
    output logic [31:0]WB_NPC,
    output logic [31:0]WB_Instr,
    output logic [4:0]WB_RW,
    output logic [1:0]WB_Data_To_Reg_Sel,
    output logic [31:0]WB_ALU_Out,
    output logic [31:0]WB_Data_From_DM,
    output logic WB_CP0Wr,
    output logic WB_DMRd,
    output ExceptionType WB_ExceptionType,
    output logic [2:0]WB_Reg_Writed,
    output logic [31:0] WB_CP0RdData
);
    always_ff @(posedge clk,negedge reset)begin
        if(!reset||MEM2_WB_Flush)begin
            WB_PC <= 32'b0;
            WB_NPC <= 32'b0;
            WB_Instr <= 32'b0;
            WB_RW <= 5'b0;
            WB_Data_To_Reg_Sel <= 2'b0;
            WB_ALU_Out <= 32'b0;
            WB_Data_From_DM <= 32'b0;
            WB_CP0Wr<=1'b0;
            WB_DMRd<=1'b0;
            WB_ExceptionType<=`NoException;
            WB_Reg_Writed<=3'b0;
            WB_CP0RdData<=32'b0;
        end
        else if(!MEM2_WB_Stall)begin
            WB_PC <= MEM2_PC;
            WB_NPC <= MEM2_NPC;
            WB_Instr <= MEM2_Instr;
            WB_RW <= MEM2_RW;
            WB_Data_To_Reg_Sel <= MEM2_Data_To_Reg_Sel;
            WB_ALU_Out <= MEM2_ALU_Out;
            WB_Data_From_DM <= Data_From_DM_AfterExt;
            WB_CP0Wr<=MEM2_CP0Wr;
            WB_DMRd<=MEM2_DMRd;
            WB_ExceptionType<=MEM2_ExceptionType;
            WB_Reg_Writed<=MEM2_Reg_Writed;
            WB_CP0RdData<=MEM2_CP0RdData;
        end
        else 
            ;
    end
endmodule